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Publications

Journal/Conference Articles

  1. Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram Adve, Luigi Nardi, Eriko Nurvitadhi, and Rob A Rutenbar, “HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming,” Proc. 33rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2022. (Shortlisted for Best Paper at ASAP22.)
  2. Adel Ejjeh, Leon Medvinski, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar “HPVM2FPGA: Enabling Hardware Agnostic FPGA Programming Through Compiler Techniques,” ACM/IEEE Design Automation Conference (DAC Poster), July ’22.
  3. Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar, “Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme, Proc. IEEE Int’l Symposium on Field Programmable Computing Machines (FCCM), July 2020.
  4. Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, Gu-Yeon Wei, David Brooks,  “A Scalable Bayesian Inference Accelerator for Unsupervised Learning,” IEEE Hot Chips Symposium, August 2020.
  5. Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei, “A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm,” Proc. IEEE 2020 Symposium on VLSI Technology, June 2020.
  6. Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, and Rob A. Rutenbar,” Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme,” in Proc. IEEE Int’l Symposium on Field Programmable Computing Machines, July 2020.
  7. Adel Ejjeh, Vikram Adve, R.A. Rutenbar, “Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL,” Abstract in Proc. 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA Poster),  Feb. 2020.
  8. Sungwoon Kim, R. A. Rutenbar, et al., “FPGA-based Accelerators for Fully Pipelined Modular Multipliers for Homomorphic Encryption,” in Proc. 2019 Int’l Conference on ReConfigurable Computing and FPGAs, December 2019, Cancun, Mexico.
  9. Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks and Gu-Yeon Wei, “Accelerating Bayesian Inference for Structured Graphs Using Parallel Gibbs Architecture,” in Proc. Int’l Conference on Field Programmable Logic & Applications (FPL), September 2019.
  10. Tianqi Gao, R.A. Rutenbar, “A Virtual Image Accelerator for Graph Cuts Inference on FPGA,” Abstract in Proc. 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP Poster), July 2019.
  11. Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks and Gu-Yeon Wei, “FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs,” Abstract in Proc. IEEE Int’l Symposium on Field Programmable Computing Machines (FCCM poster), May 2019.
  12. Sunwoong Kim, Rob A. Rutenbar, “Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for an FPGA,”in Proc. Great Lakes Symposium on VLSI, May 2019.
  13. Tianqi Gao, Rob A. Rutenbar, “A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference,”  Abstract in Proc. 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, (ISFPGA poster)  Feb. 2019.
  14. Sunwoong Kim, Rob A. Rutenbar, “Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA,” Abstract in Proc. IEEE Int’l Symposium on Field Programmable Computing Machines (FCCM poster), May 2018.
  15. Glenn G. Ko and Rob A. Rutenbar, “Real-Time and Low-Power Streaming Source Separation using Markov Random Field,” IEEE Journal of Emerging and Selected Topics in Circuits and Systems (JETCAS), Special Issue on Frontiers of Hardware and Algorithms for On-chip Learning, Vol. 14, Issue 2, May 2018.
  16. Francine Berman, Rob Rutenbar, Brent Hailpern, Henrik Christensen, Susan Davidson, Deborah Estrin, Michael Franklin, Margaret Martonosi, Padma Raghavan, Victoria Stodden, Alexander S. Szalay, “Realizing the Potential of Data Science,”  Communications of the ACM (CACM), Vol. 61 No. 4, Pages 67-72, April 15, 2018.  10.1145/3188721.
  17. Glenn Ko and Rob A. Rutenbar, “Real Time Source Separation using Probabilistic Inference,” SRC TECHCON Conference, Austin TX, Sept. 2017.
  18. Tianqi Gao, Jungwook Choi, Shang-nien Tsai and Rob A. Rutenbar, “Toward a Pixel-Parallel Architecture for Graph Cuts Inference on FPGA, 2017 International Conference on Field-Programmable Logic and Applications,  Sept. 2017. 
  19. Glenn Ko and Rob A. Rutenbar, “A Case Study of Machine Learning Hardware: Real-Time Source Separation using Markov Random Fields via Sampling-based Inference”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), April 2017.
  20. J. Choi and R.A. Rutenbar, “Configurable and Scalable Belief Propagation Accelerator for Computer Vision,” Int’l Conference on Field Programmable Logic and Applications (FPL’16), September 2016.
  21. J. Choi, A. D. Patil, R.A. Rutenbar, N. R. Shanbhag, “Analysis Of Error Resiliency Of Belief Propagation In Computer Vision,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), April 2016.
  22. Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, and Rob A. Rutenbar, “Error Resilient and Energy Efficient MRF Message Passing Based Stereo Matching,” IEEE Transactions on VLSI Systems (TVLSI), Vol. 24, No. 3, March 2016.
  23. Jungwook Choi and Rob A. Rutenbar, “Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform,” IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 26, no. 2, February 2016.
  24. Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, Jose F. Martinez, Rob A. Rutenbar, “A Fast Hierarchical Implementation of Sequential Tree reweighted Belief Propagation for Probabilistic Inference,”  in Proc. 25th International Conference on Field Programmable Logic and Applications (FPL’15) London, England, Sept. 2015.
  25. R.A. Rutenbar, “The First EDA MOOC:  Teaching Design Automation to Planet Earth,” in Proc. 2014 ACM/IEEE Design Automation Conference, June 2014. 
  26. Abner Guzman-Rivera,  Dhruv Batra, Pushmeet Kohli, Rob A. Rutenbar, “Efficiently Enforcing Diversity in Multi-Output Structured Prediction,”  in Proc. Seventeenth Int’l Conference on Artificial and Statistics (AISTATS), April 2014, Reykjavik, Iceland.
  27. Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, and Rob A. Rutenbar, “A Robust Message Passing Based Stereo Matching Kernel via System-Level Error Resiliency,” in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Apr. 2014.
  28. Rob A. Rutenbar, “DAC at 50: The Second 25 Years,” IEEE Design & Test, Vol. 31, No 2, March/April 2014.  (Paper based on 50th Anniversary DAC conference keynote,  invited to IEEE Design & Test Magazine.)
  29. Jungwook Choi and Rob. A. Rutenbar, “FPGA Acceleration of Markov Random Field TRW-S Inference for Stereo Matching”, in Proc. 2013 Eleventh IEEE/ACM Int’l Conference Formal Methods and Models for Codesign (MEMOCODE), October 2013.  (Invited paper;  Design Contest Winner in the “Adjusted Runtime” category in the MEMOCODE 2013 design contest, for our FPGA-accelerated implementation of stereo vision.)
  30. Jungwook Choi, Erik Kim, Rob A. Rutenbar, Naresh Shanbhag,  “Error Resilient MRF Message Passing Architecture for Stereo Matching”, in Proc. 2013 IEEE Workshop on Signal Processing Systems, Taipei, Taiwan from October 16-18, 2013.  (Best Student Paper Award.)
  31. Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzman-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao and Mei Chen. “EMERALD: Characterization of emerging applications and algorithms for low-power devices,” in Proc. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2013.
  32. Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane Boning, Sharad Saxena, Andrzej Strojwas and Rob A. Rutenbar, “Efficient Spatial Pattern Analysis for Variation Decomposition via Robust Sparse Regression,” IEEE Trans. On CAD, vol 32, no. 7, July 2013.
  33. Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej Strojwas, R.A. Rutenbar “A Methodology for Automatic Clustering of Wafer Spatial Signatures,” Proc. ACM/IEEE Design Automation Conference, June 2013.
  34. Jungwook Choi and Rob A. Rutenbar, “Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform,” in Proc. ACM Int’l Symposium on FPGAs (ISFPGA), February 2013.
  35. Minje Kim, Paris Smaragdis, Glenn G. Ko, and Rob A. Rutenbar,
“Stereophonic Spectrogram Segmentation Using Markov Random Fields,”
in Proc. IEEE International Workshop on Machine Learning for Signal Processing (MLSP), Santander, Spain, September 2012.
  36. Jungwook Choi and Rob A. Rutenbar, “Hardware Implementation of MRF MAP Inference on an FPGA Platform,” Proc. 22nd Intl Conference on Field Programmable Logic and Applications (FPL), August 2012.
  37. Jeffrey R. Johnston, Rob A. Rutenbar, “A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers,”  in Proc. 23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP’2012, Delft, The Netherlands, July 2012.
  38. Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane Boning, Emrah Acar, Frank Liu and Rob A. Rutenbar, “Spatial Variation Decomposition via Sparse Regression,” Proc .IEEE  International Conference on Integrated Circuit Design & Technology (ICICDT), invited, June 2012.
  39. Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar,  Rob A. Rutenbar, R. Shawn Blanton, “Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits,” IEEE Trans. On CAD, Vol. 30, No. 12, pp. 1814 – 1827, December 2011. (Winner of 2013 IEEE Donald O. Pederson Best Paper Award for Transactions on CAD.)
  40. W. Zhang, K. Balakrishnan, X. Li, D. Boning, R.A. Rutenbar, “Toward efficient spatial variation decomposition via sparse regression,” Proc ACM/IEEE International Conference on CAD (ICCAD), pp. 162-169, November 2011.
  41. Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun, “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs,” IEEE Transactions on CAD,  VOl. 29, No. 12, pp. 1908-1920, December 2010.
  42. Amith Singhee and Rob A. Rutenbar, “Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis,” IEEE Transactions on CAD, Vol. 29, No. 11, pp. 1763-1776, November 2010.
  43. Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar, “ Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation,” Proc. ACM/IEEE International Conference on CAD (ICCAD), pp. 47-54, November 2010.
  44. Wangyang Zhang, Xin Li and Rob A. Rutenbar, “Bayesian Virtual Probe: Minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference,” Proc. ACM/IEEE Design Automation Conference (DAC), pp. 262-267, July 2010. (Winner of 2010 DAC Best Paper Award.)
  45. Xin Li, Rob A. Rutenbar, R. Shawn Blanton, “Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits,”  Proc. ACM/IEEE International Conference on CAD (ICCAD),  pp. 433-440, November 2009.
  46. A. Singhee and R.A. Rutenbar, “Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design,” IEEE Trans. On CAD, Vol. 28, No. 8, pp. 1176-1189, August 2009. (Winner of 2011 IEEE Donald O. Pederson Best Paper Award for Transactions on CAD.)
  47. E.C. Lin and R.A. Rutenbar, “A Multi-FPGA 10x-Real-Time High-Speed Search Engine for a 5000-Word Vocabulary Speech Recognizer ,” Proc. 2009 ACM International Symposium on FPGAs (ISFPGA), February 2009.
  48. A. Singhee, C.F. Fang, J.D. Ma and R.A. Rutenbar, “Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools,” IEEE Transactions on CAD, Vol: 27 , No: 12, pp. 2317-2330, December 2008.
  49. P. Bourke and R.A. Rutenbar, “A Low-Power Hardware Search Architecture for Speech Recognition,” Proc. Interspeech 2008, October 2008.
  50. A. Singhee, S. Singhal, R. A. Rutenbar, “Practical, Fast Monte Carlo Statistical Static Timing Analy­sis: Why and How,” Proc. ACM/IEEE 2008 International Conference on CAD, November 2008.
  51. A. Singhee, S. Singhal, R. A. Rutenbar, “Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing,” Proc. Design Automation and Test in Europe Conference (DATE), March 2008.
  52. Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar and Kenneth L. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS,” Proceedings of the IEEE, Vol. 96, No. 2, pages 343-365, February 2008.
  53. A. Singhee, J. Wang, B. H. Calhoun, R. A. Rutenbar, “Recursive Statistical Blockade: Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design,”  Proc. 2008 International Conference on VLSI, January 2008.
  54. J. Wang, A. Singhee, R.A. Rutenbar, B. H. Calhoun, “Modeling the Minimum Standby Supply Volt­age of a Full SRAM Array,” Proc. European Solid State Circuits Conference (ESSCIRC), October 2007.
  55. James D. Ma and Rob A. Rutenbar, “Interval-Valued Reduced Order Statistical Interconnect Model­ing,”   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 9, Sept. 2007.
  56. K. Yu, R.A. Rutenbar, “Generating Small, Accurate Acoustic Models with a Modified Bayesian Information Criterion,” Proc. Interspeech 2007, August 2007.
  57. Amith Singhee and Rob A. Rutenbar, “Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting,” Proc. ACM/IEEE Design Automation Conference, June 2007.
  58. Amith Singhee and Rob A. Rutenbar, “Statistical Blockade: A Novel Method for Very Fast Money Carlo Simulation of Rare Circuit Events, and its Application," ,"  Proceedings of the 10th Conference on Design, Automation and Test in Europe (DATE 06), April 2007. (Winner, DATE2007 Best Paper.)
  59. Amith Singhee and Rob A. Rutenbar, “From Finance to Flip Flops:  A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis,” Proc. IEEE 8th International Symposium on Quality Electronic Design (ISQED), March 2007.
  60. Jaijeet Roychowdhury, Rob A. Rutenbar and Georges Gielen, “Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs,” Proceedings of the IEEE, vol. 95, no. 3, March 2007. (Invited).
  61. Zhong Xiu and Rob A. Rutenbar, “Mixed-Size Placemente with Fixed Macrocells using Grid-Warp­ing,” Proc. ACM International Symposium on Physical Design, April 2007.
  62. Edward C. Lin, Kai Yu, Rob A. Rutenbar and Tsuhan Chen, “A 1000-Word Vocabulary, Speaker- Independent, Continuous Live-Mode Speech Recognizer Implemented in a Single FPGA,” Proc. ACM International Symposium on FPGAs, Feb. 2007.
  63. Saurabh K. Tiwary and  Rob A Rutenbar, “Faster, Parametric Trajectory-based Macromodels Via Localized Linear Reductions,'   Proc. ACM/IEEE International Conference on CAD, Nov. 2006.
  64. Edward C. Lin, Kai Yu, Rob A. Rutenbar and Tsuhan Chen, “Moving Speech Recognition from Software to Silicon: the In Silico Vox Project,” Proc. International Conference on Spoken Language Process­ing (InterSpeech2006), September 2006.
  65. Saurabh K Tiwary and  Rob A Rutenbar, “On-the-Fly Fidelity Assessment for Trajectory-Based Cir­cuit Macromodels,” Proc. 2006 IEEE Custom Integrated Circuits Conference (CICC 2006), September 2006.
  66. Saurabh K Tiwary  Pragati K Tiwary  Rob A Rutenbar, “Generation of Yield Aware Pareto Surfaces for Hierarchical Design Space Exploration,” Proc. ACM/IEEE Design Automation Conference, July 2006.
  67. Amith Singhee, Claire F. Fang, James D. Ma, Rob A. Rutenbar, “Probabilistic Interval-Valued Com­putation: Toward a Practical Surrogate for Statistics Inside CAD Tools,” Proc. ACM/IEEE Design Automation Conference, July 2006.
  68. James D. Ma and Rob A. Rutenbar, “Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance,”  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 4, April 2006.
  69. G. Frehse, B. H. Krogh, and R. A. Rutenbar, “Verifying Analog Oscillator Circuits using Forward/ Backward Refinement,"  Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE 06), March 2006.
  70. James D. Ma, Claire F. Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning, “Interval Valued Modeling of Oxide Chemical-Mechanical Polishing,”  Proc. ACM/IEEE International Conference on CAD (ICCAD'05), Nov. 2005.
  71. Saurabh Tiwary, Rob A. Rutenbar, “Scalable Trajectory Methods for On-Demand Analog Macro­model Extraction,” Proc. ACM/IEEE Design Automation Conference, June 2005. (Nominated for Best Paper Award.)
  72. Zhong Xiu, Rob A. Rutenbar, “Timing-Driven Placement by Grid Warping,” Proc. ACM/IEEE Design Automation Conference, June 2005.
  73. Zhong Xiu,  David A. Papa, Philip Chong, Christoph Albrecht,  Andreas Kuehlman, Rob A. Ruten­bar, Igor L. Markov, “Early Research Experience With OpenAccess Gear: An Open Source Devel­opment Environment For Physical Design,” Proc ACM Int'l Symposium on Physical Design, April 2005 (invited).
  74. G. Frehse, B. H. Krogh, R. A. Rutenbar, and O. Maler, “Time domain verification of oscillator cir­cuit properties,”  2005 Workshop on Formal Verification of Analog Circuits (a satellite event of ETAPS 2005, April 2005, Edinburgh Scotland).
  75. James D. Ma, Rob A. Rutenbar, “Fast Interval-Valued Statistical Interconnect Modeling and Reduc­tion,” Proc. ACM Int’l Symposium on Physical Design, April 2005.
  76. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, and Tamal Mukherjee,   “Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters,”  Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE 06), March 2005.
  77. James D. Ma, Rob A. Rutenbar, “Interval-Valued Reduced Order Statistical Interconnect Modeling” Proc. ACM/IEEE Int’l Conference on CAD, Nov. 2004.
  78. Smriti Gupta, Bruce Krogh, Rob A. Rutenbar, “Towards Formal Verification of Analog Designs,” Proc. ACM/IEEE Int’l Conference on CAD, Nov. 2004.
  79. Zhong Xiu, James D. Ma, Suzanne Fowler, Rob A. Rutenbar,  “Large-Scale Placement by Grid Warping,” Proc. ACM/IEEE Design Automation Conference, June 2004.
  80. Gang Zhang, Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley, “A Synthesis Flow Towards Fast Parasitic Closure For Radio-Frequency Integrated Circuits,” Proc. ACM/IEEE Design Automation Conference, June 2004.
  81. Gi-Joon Nam, Fadi Aloul, Karem Sakallah, Rob A. Rutenbar, “A Comparative Study of Two Bool­ean Formulations of FPGA Detailed Routing,” IEEE Transaction on Computers, vol 53, no 6, June 2004.
  82. Saurabh Kumar Tiwary, Senthil Velu, Rob A Rutenbar and Tamal Mukherjee, “Pareto Optimal Modeling for Efficient PLL Optimization,” in Proc. Nanotech 2004 Conference, March 2004, Boston.
  83. Fang Fang, Markus Puschel, Rob A. Rutenbar, Tsuhan Chen, “Fast, Accurate Static Analysis for Fixed-Point Finite Precision Effects in DSP Designs,” Proc. ACM/IEEE International Conference on CAD, November 2003.
  84. Fang Fang, Markus Puschel, Rob A. Rutenbar, Tsuhan Chen, “Toward Efficient Static Analysis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling,” Proc ACM/IEEE Design Automation Conference, June 2003.
  85. Hui Xu and Rob A. Rutenbar, “sub-SAT: A formulation for Relaxed Boolean Satisfiability with Application to Routing,” IEEE Transactions on CAD, vol  22, no 6, June 2003.
  86. Hui Xu, Rob A. Rutenbar, “Insights from Almost Satisfied: Quantifying the Fine-Structure of Unsatisfiability for  the 3-SAT Phase Transition,” Sixth International Conference on Theory and Applications of Satisfiability Testing (SAT03), April 2003.
  87. Fang Fang, Tsuhan Chen, Rob A. Rutenbar, “Floating-point error analysis using affine arithmetic,” Proc. International Conference on Acoustic, Speech and Signal Processing, (ICASSP) April, 2003.
  88. Fang Fang, Tsuhan Chen, and Rob A. Rutenbar, “Lightweight Floating-Point Arithmetic:-- Case Study of Inverse Discrete Cosine Transform”, EURASIP Journal of Applied Signal Processing, Special Issue on “Implementation of DSP and Communication Systems, 3rd Quarter, 2002.
  89. Gi-Joon Nam, Karem Sakallah and Rob Rutenbar, “Hybrid Routing for FPGAs by Integrating Bool­ean Satisfiability with Geometric Search,”  Proc. 12th International Conference on Field Programmable Logic and Application (FPL02), Sept. 2-4, 2002.
  90. Hongzhou Liu, Amit Singhee, Rob A. Rutenbar and L. Richard Carley, “Remembrance of Circuits Past: Macromodeling via Data Mining in Large Analog Design Spaces,” Proc. ACM/IEEE Design Automation Conference, June 2002.
  91. Fang Fang, Tsuhan Chen, and Rob A. Rutenbar, “Floating-Point Bit-Width Optimization for Low- Power Signal Processing Application”, Proc. IEEE ICASSP 2002, April 2002.
  92. Hui Xu and Rob A. Rutenbar, “sub-SAT: A formulation for Relaxed Boolean Satisfiability with Application to Routing,” Proc. ACM International Symposium on Physical Design, April 2002.
  93. Rob A. Rutenbar, “Structured Simulation-Based Analog Design Synthesis,” in Proc. Advances in Ana­log Circuit Design Workshop, Spa, Belgium, March 2002.
  94. Gi-Joon Nam, Karem A. Sakallah, and Rob A. Rutenbar, “A New FPGA Detailed Routing Approach Via Search-Based Boolean Satisfiability,” IEEE Transactions on CAD, vol 21, no. 6, 2002.
  95. D. Leenaerts, G.G.E Gielen, R.A. Rutenbar, “CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design,” Proc. ACM/ IEEE ICCAD, Nov. 2001. (Invited Tutorial Paper)
  96. Michael J. Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, and L. Richard Carley, “ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Ana­log Circuits,” Proc. ACM/IEEE International Conference on CAD, November 2001.
  97. Prakash Gopalakrishnan and Rob A. Rutenbar, “Direct Transistor-Level Layout for Digital Blocks,” Proc. ACM/IEEE International Conference on CAD, November 2001.
  98. Nicola Dragone, L. Richard Carley, Rob A. Rutenbar, Roberto Zafalon, “Low-Power Technology Mapping for Mixed-Swing Logic,” Proc. IEEE International Symposium on Low-Power Electronic Devices (ISLPED), August 2001.
  99. Rony Kay and Rob A. Rutenbar, “Wire Packing: A Strong Formulation of Crosstalk-Aware Chip- Level Track/Layer Assignment with an Efficient Integer Programming Solution,” IEEE Trans. CAD, vol. 20, no. 5, May 2001, pp 672 -679.
  100. Gi-Joon Nam, Fadi Aloul, Karem Sakallah, Rob A. Rutenbar, “A Comparative Study of Two Bool­ean Formulations of FPGA Detailed Routing Constraints,” Proc. ACM International Symposium on Physical Design (ISPD2001), April 2001.
  101. Gi-Joon Nam, Karem Sakallah, Rob A. Rutenbar, “A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs,” Proc. Design Automation & Test Europe (DATE2001), March 2001.
  102. Georges Gielen and Rob A. Rutenbar, “Computer Aided Design of Analog & Mixed Signal Inte­grated Circuits,” Proceedings of the IEEE, vol. 88, no.12, December 2000.
  103. Prakash Gopalakrishnan and Rob A. Rutenbar, “Direct Transistor-Level Placement,” Proc. Semicon­ductor Research Corporation (SRC) Techcon, October 2000.
  104. Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar, “Efficient Handling of Operating Range and Manufacturing Line Variations in Analog Cell Synthesis,” IEEE Transactions on CAD, vol. 18, no. 8, August 2000.
  105. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, “A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC,” Proc. ACM/IEEE Design Automation Conference, June 2000.
  106. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums, “Ana­conda: Simulation-Based Synthesis of Analog Circuits Via Stochastic Pattern Search,” IEEE Transac­tions on CAD, vol. 18, no. 6, June 2000.
  107. Jonathan Ying-Fai Tong, David Nagle, Rob A. Rutenbar, “Reducing Power By Optimizing the Nec­essary Precision/Range of Floating-Point Arithmetic,” IEEE Transactions on VLSI, vol. 8, no. 3, June 2000.
  108. Rob A. Rutenbar and John M. Cohn, “Layout Tools for Analog ICs and Mixed-Signal SoCs: A Sur­vey,” Proc. ACM International Symposium on Physical Design, April 2000.
  109. Rony Kay and Rob A. Rutenbar, “Wire Packing: A Strong Formulation of Crosstalk-Aware Chip- Level Track/Layer Assignment with an Efficient Integer Programming Solution,” Proc. ACM Interna­tional Symposium on Physical Design, April 2000.
  110. Pascal Meier, Rob A. Rutenbar, L. Richard Carley, “Inverse Polarity Techniques for High-Speed/ Low-Power Multipliers,” Proc. International Symposium on Low-Power Electronics and Design, August 1999.
  111. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells,” in Proc. ACM/IEEE Design Automation Con­ference, June 1999.
  112. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, J.R. Hellums, “ANA­CONDA: Robust Synthesis of Analog Circuits Via Stochastic Pattern Search,” in Proc. IEEE Custom Integrated Circuits Conference, May 1999.
  113. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley “Transistor-Level Early Floorplanning Algo­rithms for RF Circuits,” IEEE Transactions on CAD, March 1999.
  114. Gi-Joon Nam, Karem Sakallah, Rob A. Rutenbar, “Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs Via Search-Based SAT,” in Proc. ACM International Symposium on FPGAs, February 1999.
  115. Gi-Joon Nam, Karem Sakallah, Rob A. Rutenbar, “Satisfiability-Based Detailed FGPA Routing,” in Proc. International Conference on VLSI, January 1999.
  116. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley, “A Layout Approach for  RF Circuits with Tight Constraints,” Semiconductor Research Corporation TECHCON'98 Conference (abstracts), September 1998.
  117. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “Generalized Analog Circuit Synthesis,” Semiconductor Research Corporation TECHCON'98 Conference (abstracts), Septem­ber 1998.
  118. Ying-Fai Tong, Rob A. Rutenbar, David Nagle, “Minimizing Floating Point Power Dissipation via Bitwidth Reduction,” Proceedings Power-Driven Microarchitecture Workshop, held at ACM International Symposium on Computer Architecture, 1998.
  119. Sudip K. Nag and Rob A. Rutenbar, “Performance-Directed Simultaneous Placement and Routing for FPGAs,” IEEE Transactions on CAD, vol. 17, no. 6, June 1998.
  120. Glenn Wood and Rob A. Rutenbar, “FPGA Routing and Routability Estimation via Boolean Satisfi­ability,” IEEE Transactions on VLSI, vol. 6, no. 2, June 1998.
  121. Mehmet Aktuna, Rob A. Rutenbar and L. Richard Carley, “Device Level Early Floorplanning for RF Circuits,” in Proc. 1998 ACM International Symposium on Physical Design, April 1998.
  122. Gary Ellis, Lawrence Pileggi and Rob A. Rutenbar, “A Hierarchical Decomposition Methodology for Multi-Stage Clock Circuits,” in Proc. 1997 ACM/IEEE International Conference on CAD, November 1997.
  123. Gary Ellis, Lawrence Pileggi and Rob A. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits,” in Proc. 1997 IEEE Custom Integrated Circuits Conference, May 1997.
  124. R. Glenn Wood and Rob A. Rutenbar, “FPGA Routing and Routability Estimation via Boolean Sat­isfiability,” Proc. ACM International Symposium on FPGAs, February 1997.
  125. A. Kolli, J. Cagan, and R. A. Rutenbar, “Packing of Generic, Three-Dimensional Components Based on Multi-Resolution Modeling,” Proc. 1996 ASME Design Automation Conference, August 1996.
  126. L. Richard Carley, Georges Gielen, Rob A. Rutenbar, Willy Sansen, “Synthesis Tools for Mixed-Sig­nal ICs: Progress on Frontend and Backend Strategies,” tutorial paper in Proc. 1996 ACM/IEEE Design Automation Conference, June 1996.
  127. Bulent Basaran and Rob A. Rutenbar, “An O(n) Algorithm for Optimum CMOS Device Stacking with Analog Constraints,” Proc. ACM/IEEE Design Automation Conference, June 1996.
  128. Pascal Meier, Rob A. Rutenbar and L. Richard Carley, “Exploring Multiplier Architecture and Lay­out for Low Power,” Proc. IEEE Custom IC Conference, May 1996.
  129. Bulent Basaran and Rob A. Rutenbar, “Efficient Area Minimization for Dynamic CMOS Circuits,” Proc. IEEE Custom IC Conference, May 1996.
  130. Bulent Basaran and Rob A. Rutenbar, “Efficient Area Minimization for Dynamic CMOS Circuits,” Proc. ACM Physical Design Workshop, April 1996.
  131. Bulent Basaran and Rob A. Rutenbar, “An O(n) Algorithm for Transistor Stacking with Perfor­mance Constraints,” Proc. ACM Physical Design Workshop, April 1996.
  132. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” IEEE Transactions on CAD, vol. 15, no. 3, March 1996.
  133. S.K. Nag and R.A. Rutenbar, “Performance-Directed Simultaneous Place and Route for Island-Style FPGAs,”   Proc. 1995 ACM/IEEE International Conference on CAD, November 1995.
  134. S.W. Director, P.K. Khosla, R.A. Rohrer, R.A. Rutenbar, “Reengineering the Curriculum: Design and Implementation of a New B.S. Degree in Electrical and Computer Engineering at Carnegie Mel­lon,” Proceedings of the IEEE, vol. 83, no. 9, September 1995.
  135. L.R. Carley, R. A. Rutenbar, et al., “Optimization-based Layout of Analog ICs,” Proc. Systematic Ana­log Design II Workshop, Leuven, Belgium, June 1995.
  136. L.R. Carley, R. A. Rutenbar, et al., “Synthesis of High Performance Analog Cells in ASTRX OBLX,” Proc. Systematic Analog Design II Workshop, June 1995.
  137. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “A Methodology for Rapid Estimation of Sub­strate-Coupled Switching Noise,” in Proc. 1995 IEEE Custom IC Conference, May 1995.
  138. R. A. Rutenbar and L.R. Carley, et al., “Synthesis and Layout for Analog and Mixed Signal ICs in the ACACIA System,” Proc. Advances in Analog Circuit Design Workshop, April 1995.
  139. P.C. Maulik, L.R. Carley and R.A. Rutenbar “Simultaneous Topology Selection and Sizing of Cell- level Analog Circuits,” IEEE Transactions on Computer Aided Design, vol. 14, no. 4, April 1995.
  140. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” IEEE Journal of Solid   State Circuits, vol. 30, no. 3, March 1995.
  141. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” IEEE Journal of Solid   State Circuits, vol. 30, no. 3, March 1995.
  142. P. Nag, J. Khare, S. Mitra, W. Maly and R.A. Rutenbar, “A Testability Oriented Channel Router,” in Proc. 1995 Indian VLSI Conference, India, Jan. 1995.
  143. S.K. Nag and R.A. Rutenbar, “Performance-Directed Simultaneous Place and Route for Row-Based FPGAs,” Proceedings 1994 ACM/IEEE Design Automation Conference, June 1994.
  144. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” Proceedings 31st ACM/IEEE Design Automation Conference, June 1994.
  145. E.S. Ochotta, L.R. Carley and R.A. Rutenbar “Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Converter with ASTRX/OBLX,” Proceedings IEEE Custom Integrated Cir­cuits Conference, May 1994.
  146. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” Proceedings 1994 IEEE Custom Integrated Circuits Conference, May 1994.
  147. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” Proceedings 1994 IEEE Custom Inte­grated Circuits Conference, May 1994.
  148. B.R. Stanisic, N.K. Verghese, D.J. Allstot, R.A. Rutenbar, L.R. Carley, “Addressing Substrate Cou­pling in Mixed-Mode ICs: Simulation and Power Distribution Synthesis,” IEEE Journal of Solid State Circuits, vol 29, no. 3, March 1994.
  149. B. Basaran, R.A. Rutenbar and L.R. Carley, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells,” Proceedings ACM/IEEE International Conference on CAD, November 1993.
  150. S. Mitra, B. Basaran, S.K. Nag, B.R. Stanisic, “Analog and Mixed-Signal Layout at CMU: From Cells to Systems,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’93, Sept. 1993.
  151. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “Bridging the Gap Between Analog Designers and Analog Synthesis Tools with ASTRX/OBLX,” Extended Abstract Volume, Semiconductor Research Corpo­ration TECHCON’93, Sept. 1993.
  152. R. A. Rutenbar, “Analog Design Automation: Where are We? Where are we Going?” in Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993 (invited).
  153. B. R. Stanisic, R. A. Rutenbar and L. Richard Carley, “Power Distribution Synthesis for Analog and Mixed-Signal ASICs in RAIL,” Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993.
  154. S. Mitra, S.K. Nag, R.A. Rutenbar and L.R. Carley, “System-Level Routing of Mixed-Signal ASICs in WREN,” Proceedings ACM/IEEE International Conference on CAD (ICCAD’92), November 1992.
  155. P.C. Maulik, L.R. Carley, R.A. Rutenbar, “A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis,” Proceedings ACM/IEEE Design Automation Conference, June 1992.
  156. D. Setliff and R. A. Rutenbar, “Knowledge Representation and Reasoning in a Software Synthesis Architecture,” IEEE Transactions on Software Engineering, vol. 17, no. 6, June 1992.
  157. L. R. Carley, P. C. Maulik, E. S. Ochotta, and R. A. Rutenbar, “Analog Cell-Level Synthesis Using a Novel Problem Formulation,” Proceedings of Workshop on Advances in Analog Circuit Design, T. U. Delft, The Netherlands, April 1992.
  158. E. Ochotta, R.A. Rutenbar and L.R. Carley, “Equation-Free Synthesis of High-Performance Linear Analog Circuits,” in Advanced Research in VLSI and Parallel Systems, T. Knight and J. Savage (eds.), pp. 129-146, Cambridge MA, MIT Press, March 1992.
  159. R. Jayaraman and R. A. Rutenbar, “A Parallel Steiner Heuristic for Wirelength Approximation of Large Net Populations,” Proceedings 1991 IEEE International Conference on Computer Aided Design (ICCAD’91), Nov. 1991.
  160. J. Cohn, D. Garrod, R. A. Rutenbar, and L. R. Carley, “Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II,” Proceedings 1991 IEEE International Conference on Computer Aided Design (ICCAD’91), Nov. 1991.
  161. S.A. Kravitz, R.E. Bryant and R.A. Rutenbar, “Massively Parallel Switch-Level Simulation: A Feasi­bility Study,” IEEE Transactions on CAD of ICs and Systems, vol. 10, no. 7, June 1991.
  162. D. Setliff and R. A. Rutenbar, “On the Feasibility of Synthesizing CAD Software From Specifica­tions: Generating Maze-Routers in ELF,” IEEE Transactions on CAD of ICs and Systems, vol. 10, no. 6, June 1991.
  163. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “KOAN / ANAGRAM II: New Techniques for Device-Level Analog Placement and Routing,” IEEE Journal of Solid State Circuits, vol. 26, no. 3, February 1991.
  164. E. Ochotta, P.C. Maulik, T. Mukherjee, H. Malik, L.R. Carley, and R.A. Rutenbar, “The Evolution of the OASYS Analog Synthesis Tool,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’90, October, 1990.
  165. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “KOAN/ANAGRAM II: Flexible Algorithms for Layout of Custom Analog Cells,” Extended Abstract Volume, Semiconductor Research Corporation TECHCON’90, October, 1990.
  166. E. C. Carlson and R. A. Rutenbar, “Design and Performance Evaluation of New Massively Parallel Mask Verification Algorithms in JIGSAW,” Proceedings 27th ACM/IEEE Design Automation Confer­ence, June 1990.
  167. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “New Algorithms for Placement and Routing of Custom Analog Cells in ACACIA,” in Proceedings IEEE Custom Integrated Circuits Conference (CICC’90), May 1990.
  168. Rob A. Rutenbar and Kit Tham, “Design Automation: Even When It’s Old It’s New,” IEEE Design & Test of Computers, vol. 6, no. 6, pp. 4-5, December 1989. (Guest Editors’ introduction to special issue of journal devoted to best papers from 1989 ACM/IEEE Design Automation Conference.)
  169. R. Harjani, R. A. Rutenbar and L. R. Carley, “OASYS: A Framework for Analog Circuit Synthesis,” IEEE Transactions on CAD of ICs and Systems, vol 8, no. 12, Dec. 1989.
  170. R. A. Rutenbar, “Zen and the Art of Analog Design Automation,” Proceedings IFIP World Computer Congress ‘89, August 1989.
  171. R. A. Rutenbar, “The Evolution of Knowledge-Based CAD Tools: A Carnegie Mellon Perspective,” Proceedings IFIP (WG10.2) Working Conference on CAD Systems Using AI Techniques, June 1989.
  172. D. Setliff and R. A. Rutenbar, “ELF: A Tool for Automatic Synthesis of Custom CAD Software,” Proceedings 26th ACM/IEEE Design Automation Conference, June 1989.
  173. S.A. Kravitz, R.E. Bryant and R.A. Rutenbar, “Massively Parallel Switch Level Simulation: A Feasi­bility Study,” Proceedings 26th ACM/IEEE Design Automation Conference, June 1989.
  174. L.R. Carley, D. Garrod, R. Harjani, J. Kelly, T. Lim, E. Ochotta and R.A. Rutenbar, “ACACIA: the CMU Analog Design System,” Proceedings IEEE Custom Integrated Circuits Conference (CICC’89), May 1989.
  175. S.A. Kravitz, R.E. Bryant and R.A. Rutenbar, “Logic Simulation on Massively Parallel Architec­tures,” Proceedings ACM/IEEE International Symposium on Computer Architecture, May 1989.
  176. R. A. Rutenbar, “Simulated Annealing Algorithms: an Overview,” IEEE Circuits and Devices Magazine, vol. 5, no. 1, January 1989.
  177. D. Garrod, R. A. Rutenbar and L. R. Carley, “Automatic Layout of Custom Analog Cells in ANA­GRAM,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’88), November 1988.
  178. R. Harjani, R. A. Rutenbar and L. R. Carley, “Analog Circuit Synthesis for Performance in OASYS,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’88), November 1988.
  179. D. Garrod, R. A. Rutenbar and L. R. Carley, “Automated Layout of Custom Analog Cells,” Extended Abstract Volume, Semiconductor Research Corporation Techcon’88, Oct. 1988.
  180. R. Harjani, R. A. Rutenbar and L. R. Carley, “Analog Circuit Synthesis for Performance in OASYS,” Extended Abstract Volume, Semiconductor Research Corporation. Techcon’88, Oct. 1988.
  181. R. Harjani, R. A. Rutenbar and L. R. Carley, “Analog Circuit Synthesis and Exploration in OASYS,” Proceedings International Conference on Computer Design (ICCD’88), October 1988.
  182. D. Setliff and R. A. Rutenbar, “Integrating Domain Knowledge and Generic Program Synthesis Knowledge: A Case Study of Software Synthesis for VLSI Design Tools,” Proceedings AAAI Work­shop on Automating Software Design, August 1988.
  183. L. R. Carley and R. A. Rutenbar, “How to Automate Analog IC Designs,” IEEE Spectrum, vol. 25, no. 8, pp. 26-30, August, 1988.
  184. E. C. Carlson and R. A. Rutenbar, “Mask Verification on the Connection Machine,” Proceedings 25th ACM/IEEE Design Automation Conference, June 1988.
  185. D. E. Setliff and R. A. Rutenbar, “Knowledge-Based Synthesis of Custom VLSI Physical Design Tools: First Steps,” Proceedings Fourth AAAI/IEEE Conference on Artificial Intelligence Applications, March 1988.
  186. R. A. Rutenbar and D. E. Atkins, “Systolic Routing Hardware: Performance Evaluation and Optimi­zation,” IEEE Transactions on CAD of ICs and Systems, vol. CAD-7, no. 7, March 1988.
  187. R. Jayaraman and R. A. Rutenbar, “Floorplanning by Annealing on a Hypercube Multiprocessor,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’87), November 1987.
  188. E. Carlson and R. A. Rutenbar, “A Scanline Data Structure Processor for VLSI Geometry Check­ing,” IEEE Transactions on CAD of ICs and Systems, vol. CAD-6, no. 5, September 1987.
  189. S. A. Kravitz and R. A. Rutenbar, “Placement by Simulated Annealing on a Multiprocessor,” IEEE Transactions on CAD of ICs and Systems, vol. CAD-6, no. 4, pp. 534-549, July 1987.
  190. R. Harjani, R. A. Rutenbar and L. R. Carley, “A Prototype Framework for Knowledge-Based Analog Circuit Synthesis,” Proceedings 24th ACM/IEEE Design Automation Conference, pp. 42-49, June-July 1987.
  191. E. Carlson and R. A. Rutenbar, “A Data-Structure Processor for VLSI Geometry Checking,” Proceed­ings ACM/IEEE International Conference on Computer Aided Design (ICCAD’86), November 1986.
  192. R. A. Rutenbar and S. Kravitz, “Layout by Annealing in a Parallel Environment,” Proceedings Interna­tional Conference on Computer Design (ICCD), October 1986.
  193. S. A. Kravitz and R. A. Rutenbar, “Multiprocessor-Based Placement by Simulated Annealing,” Pro­ceedings ACM/IEEE 23rd Design Automation Conference, Las Vegas, pp. 567-573, June 1986.
  194. R. A. Rutenbar and R. Harjani, “Synthesis of Analog VLSI Modules,” IEEE Software, vol. 3, no. 2, p. 58, March 1986. (In review section “Knowledge Based Engineering Systems: Research in Progress,” D. Sriram and M. Rychner, eds., pp. 48-60.
  195. R. A. Rutenbar, “Future Directions for DA Machine Research,” Proceedings ACM/IEEE 22nd Design Automation Conference, pp. 496-497, June 1985.
  196. S. W. Director, W. Maly, R. A. Rutenbar, J. P. Shen, D. P. Siewiorek, A. J. Strojwas, and D. E. Tho­mas, “Integrated CAD, CAT and CAM of VLSI Circuits and Systems: the CMU Perspective,” IEEE Design & Test of Computers, vol. 2, no. 3, pp. 87-100, June 1985.
  197. R. A. Rutenbar, T. N. Mudge and D. E. Atkins, “A Class of Cellular Architectures to Support Phys­ical Design Automation,” IEEE Transactions on CAD of ICs and Systems, vol. CAD-3, no. 4, pp. 264- 278, October 1984.
  198. R. A. Rutenbar, T. N. Mudge and D. E. Atkins, “Wire Routing Experiments on a Raster Pipeline Subarray Machine,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’83), Santa Clara, pp. 135-136, September 1983.
  199. T. N. Mudge, R. A. Rutenbar, R. L. Lougheed and D. E. Atkins, “Cellular Image Processing Tech­niques for VLSI Circuit Layout Validation and Routing,” Proceedings ACM/IEEE 19th Design Auto­mation Conference, Las Vegas, pp. 537-543, June 1982.
  200. R. A. Rutenbar and Y. Park, “Case Study of a VLSI Design Project: a Simple Inner Product Machine,” Proceedings IEEE 5th Symposium on Computer Arithmetic, Ann Arbor, pp. 184-189, May 1981.

Books/Chapters

  1. Jun Tao, Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton, Xuan, Zeng, “Efficient Process Variation Characterization by Virtual Probe,” chapter in Machine Learning in VLSI Computer Aided Design, Eds. Ibrahim Elfadel and Duane S. Boning, Springer Cham, 2019. ISBN 978-3-030-04666-8.
  2. Rob A. Rutenbar, John M. Cohn, Mark P.-H. Lin, and “Layout Tools for Analog Integrated Circuits and Mixed-Sig­nal Systems on Chip: A Survey,”   Chapter 16 in EDA for IC Implementation, Circuit Design and Pro­cess Technology,  2nd edition, Luciano Lavagno, Grant Martin and Louis Scheffer, eds., CRC Press, 2016. ISBN-13: 978-1482254501.
  3. Patrick Bourke, Kai Yu and Rob A. Rutenbar, “Mobile Speech Hardware: The Case for Custom Silicon,” Chapter 2 in Speech in Mobile and Pervasive Environments, Nitendra Rajput and Amit Anil Nanavati, Eds., Wiley, February 2012, pp. 7-56, 2012. ISBN:  0470694351.
  4. Robert C,. Aitken, Amith Singhee and Rob A. Rutenbar, “Extreme Value Theory: Application to Memory Statistics,” Chapter 8 in Extreme Statistics in Nanoscale Memory Design, Amith Singhee and Rob A. Rutenbar (Eds.), pp. 203-240, Springer, 2010. ISBN: 1441966056.
  5. Amith Singhee, Rob A. Rutenbar, “Statistical Blockade: Estimating Rare Event Statistics for Memories”, Chapter 9 in Embedded Memories for Nano-Scale VLSIs, Integrated Circuits and Systems Series, Springer, Kevin Zhang (Ed.), pp 329-382, 2009, ISBN: 1441946942.
  6. Rob A. Rutenbar and John M. Cohn, “Layout Tools for Analog Integrated Circuits and Mixed-Sig­nal Systems: A Survey,” Chapter 16 in EDA for IC Implementation, Circuit Design and Pro­cess Technology,  Luciano Lavagno, Grant Martin and Louis Scheffer, eds., CRC Press, 2006. ISBN 0849379245.
  7. R. A. Rutenbar, “Structured Simulation-Based Analog Design Synthesis,” chapter in Analog Circuit Design­: Structured Mixed-Mode Design, Multi-Bit Sigma-Delta Converters, Short Range RF Cir­cuits, Michiel Steyaert, Arthur H.M. van Roermund, Johan H. Huijsing, eds., Kluwer Academic Publishers, Boston: MA, August 2002, ISBN: 1-4020-7216-3.
  8. Georges G.E. Gielen and Rob A. Rutenbar, “Synthesis of Analog and Mixed-Signal Integrated Elec­tronic Circuits,” chapter in Formal Design Synthesis, E. K. Antonsson and J. Cagan, eds., Cambridge Uni­versity Press, 2001, ISBN: 0521792479.
  9. R. A. Rutenbar, L.R. Carley, et al., chapter in “Synthesis and Layout for Analog and Mixed Signal ICs in the ACACIA System,” in Analog Circuit Design--Low-Noise, Low-Power, Low-Voltage; Mixed- Mode Design with CAD Tools; Voltage, Current and Time References, Johan H. Huijsing, Rudy J. van de Plassche, Willy M.C. Sansen, eds., Kluwer Academic Publishers, Boston: MA, December 1995, ISBN: 0-7923-9659-6.
  10. L. R. Carley, P. C. Maulik, E. S. Ochotta, and R. A. Rutenbar, “Analog Cell-Level Synthesis Using a Novel Problem Formulation,” chapter in Analog Circuit Design--Operational Amplifiers, Analog to Dig­ital Convertors, Analog Computer Aided Design, Johan H. Huijsing, Rudy J. van de Plassche, Willy M.C. Sansen, eds., Boston, MA: Kluwer Academic Press, Dec. 1992, ISBN: ISBN 0-7923- 9288-4.
  11. R. A. Rutenbar, “The Evolution of Knowledge-Based CAD Tools: A Carnegie Mellon Perspective,” chapter in CAD Systems Using AI Techniques, G. Odawara, ed., North-Holland, 1989.
  12. Amith Singhee and Rob A. Rutenbar, eds., Extreme Statistics in Nanoscale Memory Design, 273pp, Springer, 2010. ISBN: 1441966056.
  13. Amith Singhee and Rob A. Rutenbar, Novel Algorithms for Fast Statistical Analysis of Scaled Circuits, 201pp, Springer (Lecture Notes in Electrical Engineering), 2009. ISBN: 9048130999.
  14. Prakash Gopalakrishnan and Rob A. Rutenbar, Direct Transistor-Level Layout for Digital Blocks, 180pp, Kluwer Academic Publishers, Boston MA, 2004. ISBN: 1402076657.
  15. Rob A. Rutenbar, Georges G.E. Gielen, Brian Antao, eds., Computer Aided Design of Analog Integrated Circuits and Systems, IEEE Press and Wiley-Interscience, 2002, ISBN: 047122782X.
  16. Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L. Richard Carley, Practical Synthesis of High-Performance Analog Circuits, Kluwer Academic Publishers, Boston: MA, 1998. ISBN: 0792382374.
  17. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic Publishers, Norwell: MA, 1996. ISBN: 0792397347.
  18. J.M. Cohn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, Analog Device-Level Layout Automa­tion, 285 pp., Kluwer Academic Publishers, Boston, MA, 1994. ISBN: 0-7923-9431-3.
  19. D. E. Setliff and R. A. Rutenbar, Automatic Programming Applied to VLSI CAD Software: A Case Study, Kluwer Academic Publishers, Boston, MA, 1990. ISBN: 0792391128.