Analog CAD

CAD rendering

Logic synthesis and ASIC layout tools makeit possible for very small teams to design very complex digital circuits. In the analog domain, such tools are still much harder to design and deploy. Our group pioneered many of the key breakthroughs that became the first generation of viable, analog circuit and layout synthesis tools. We developed many of thefirst successful analog sizing, optimization, placement, routing, and design centering tools, and explored a range of new ideas in analog modeling, pareto optimization, simulation and verification. Much of this technology was commercialized in the startup company Neolinear Inc., which was acquiredby Cadence Design Systems. Today, many of these ideas are part of the infrastructure of the industry-leading Cadence Virtuoso platform.

Key Papers

General Surveys

  1. Rob A. Rutenbar, John M. Cohn, Mark P.-H. Lin, “Layout Tools for Analog Integrated Circuits and Mixed-Sig­nal Systems on Chip: A Survey,”  Chapter 16 in EDA for IC Implementation, Circuit Design and Pro­cess Technology,  2ndedition, Luciano Lavagno, Grant Martin and Louis Scheffer, eds., CRC Press, 2016. ISBN-13: 978-1482254501.
  2. Jaijeet Roychowdhury, Rob A. Rutenbar and Georges Gielen, “Hierarchical Modeling, Optimization and Synthesis for System-Level Analog and RF Designs,” Proceedings of the IEEE, vol. 95, no. 3, March 2007. 
  3. Rob A. Rutenbar, Georges G.E. Gielen, Brian Antao, eds., Computer Aided Design of Analog Integrated Circuits and Systems, IEEE Press and Wiley-Interscience, 2002, ISBN: 047122782X.
  4. D. Leenaerts, G.G.E Gielen, R.A. Rutenbar, “CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design,”Proc. ACM/ IEEE ICCAD, Nov. 2001. (Invited Tutorial Paper)
  5. Georges Gielen and Rob A. Rutenbar, “Computer Aided Design of Analog & Mixed Signal Inte­grated Circuits,” Proceedings of the IEEE, vol. 88, no.12, December 2000.
  6. Rob A. Rutenbar and John M. Cohn, “Layout Tools for Analog ICs and Mixed-Signal SoCs: A Sur­vey,” Proc. ACM International Symposium on Physical Design, April 2000.
  7. L. Richard Carley, Georges Gielen, Rob A. Rutenbar, Willy Sansen, “Synthesis Tools for Mixed-Sig­nal ICs: Progress on Frontend and Backend Strategies,” tutorial paper in Proc. 1996 ACM/IEEE Design Automation Conference, June 1996.
  8. R. A. Rutenbar, “Analog Design Automation: Where are We? Where are we Going?” in Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993 (invited).
  9. L. R. Carley and R. A. Rutenbar, “How to Automate Analog IC Designs,” IEEE Spectrum, vol. 25, no. 8, pp. 26-30, August, 1988. 

 

Circuit Synthesis and Design Exploration

  1. Saurabh K Tiwary  Pragati K Tiwary  Rob A Rutenbar, “Generation of Yield Aware Pareto Surfaces for Hierarchical Design Space Exploration,” Proc. ACM/IEEE Design Automation Conference, July 2006.
  2. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, and Tamal Mukherjee,   “Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters,”  Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE 06), March 2005.
  3. Gang Zhang, Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley, “A Synthesis Flow Towards Fast Parasitic Closure For Radio-Frequency Integrated Circuits,” ProcACM/IEEE Design Automation Conference, June 2004.
  4. Hongzhou Liu, Amit Singhee, Rob A. Rutenbar and L. Richard Carley, “Remembrance of Circuits Past: Macromodeling via Data Mining in Large Analog Design Spaces,” Proc. ACM/IEEE Design Automation Conference, June 2002.
  5. Michael J. Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, and L. Richard Carley, “ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Ana­log Circuits,” Proc. ACM/IEEE International Conference on CAD, November 2001.
  6. Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar, “Efficient Handling of Operating Range and Manufacturing Line Variations in Analog Cell Synthesis,” IEEE Transactions on CAD, vol. 18, no. 8, August 2000.
  7. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, “A Case Study of Synthesis for Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC,” Proc. ACM/IEEE Design Automation Conference, June 2000.
  8. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums, “Ana­conda: Simulation-Based Synthesis of Analog Circuits Via Stochastic Pattern Search,” IEEE Transac­tions on CAD, vol. 18, no. 6, June 2000.
  9. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley “MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells,” in Proc. ACM/IEEE Design Automation Con­ference, June 1999.
  10. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, J.R. Hellums, “ANA­CONDA: Robust Synthesis of Analog Circuits Via Stochastic Pattern Search,” in Proc. IEEE Custom Integrated Circuits Conference, May 1999.
  11. Emil S. Ochotta, Tamal Mukherjee, Rob A. Rutenbar, L. Richard Carley, Practical Synthesis of High-Performance Analog Circuits, Kluwer Academic Publishers, Boston: MA, 1998. ISBN: 0792382374.
  12. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” IEEE Transactions on CAD, vol. 15, no. 3, March 1996.
  13. P.C. Maulik, L.R. Carley and R.A. Rutenbar “Simultaneous Topology Selection and Sizing of Cell- level Analog Circuits,” IEEE Transactions on Computer Aided Design, vol. 14, no. 4, April 1995.
  14. E.S. Ochotta, R.A. Rutenbar and L.R. Carley, “ASTRX/OBLX: Tools for Rapid Synthesis of High- Performance Analog Circuits,” Proceedings 31st ACM/IEEE Design Automation Conference, June 1994.
  15. E.S. Ochotta, L.R. Carley and R.A. Rutenbar “Analog Circuit Synthesis for Large, Realistic Cells: Designing a Pipelined A/D Converter with ASTRX/OBLX,” Proceedings IEEE Custom Integrated Cir­cuits Conference, May 1994.
  16. B. Basaran, R.A. Rutenbar and L.R. Carley, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells,” Proceedings ACM/IEEE International Conference on CAD, November 1993.
  17. P.C. Maulik, L.R. Carley, R.A. Rutenbar, “A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis,” Proceedings ACM/IEEE Design Automation Conference, June 1992.
  18. R. Harjani, R. A. Rutenbar and L. R. Carley, “OASYS: A Framework for Analog Circuit Synthesis,” IEEE Transactions on CAD of ICs and Systems, vol 8, no. 12, Dec. 1989.
  19. L.R. Carley, D. Garrod, R. Harjani, J. Kelly, T. Lim, E. Ochotta and R.A. Rutenbar, “ACACIA: the CMU Analog Design System,” Proceedings IEEE Custom Integrated Circuits Conference (CICC’89), May 1989.
  20. R. Harjani, R. A. Rutenbar and L. R. Carley, “Analog Circuit Synthesis for Performance in OASYS,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’88), November 1988. 
  21. R. Harjani, R. A. Rutenbar and L. R. Carley, “A Prototype Framework for Knowledge-Based Analog Circuit Synthesis,” Proceedings 24th ACM/IEEE Design Automation Conference, pp. 42-49, June-July 1987.

 

Physical Design

  1. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley “Transistor-Level Early Floorplanning Algo­rithms for RF Circuits,” IEEE Transactions on CAD, March 1999.
  2. Mehmet Aktuna, Rob A. Rutenbar and L. Richard Carley, “Device Level Early Floorplanning for RF Circuits,” in Proc. 1998 ACM International Symposium on Physical Design, April 1998.
  3. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic Publishers, Norwell: MA, 1996. ISBN: 0792397347.
  4. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” IEEE Journal of Solid   State Circuits, vol. 30, no. 3, March 1995. 
  5. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” IEEE Journal of Solid   State Circuits, vol. 30, no. 3, March 1995.
  6. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” Proceedings 1994 IEEE Custom Integrated Circuits Conference, May 1994. 
  7. J.M. Cohn, D.J. Garrod, R.A. Rutenbar and L.R. Carley, Analog Device-Level Layout Automa­tion285 pp., Kluwer Academic Publishers, Boston, MA, 1994. ISBN: 0-7923-9431-3.
  8. B.R. Stanisic, R.A. Rutenbar and L.R. Carley, “Mixed-Signal Noise Decoupling via Simultaneous Power Distribution Design and Cell Customization in RAIL,” Proceedings 1994 IEEE Custom Inte­grated Circuits Conference, May 1994.
  9. B.R. Stanisic, N.K. Verghese, D.J. Allstot, R.A. Rutenbar, L.R. Carley, “Addressing Substrate Cou­pling in Mixed-Mode ICs: Simulation and Power Distribution Synthesis,” IEEE Journal of Solid State Circuitsvol 29, no. 3, March 1994.
  10. B. Basaran, R.A. Rutenbar and L.R. Carley, “Latchup-Aware Placement and Parasitic-Bounded Routing of Custom Analog Cells,” Proceedings ACM/IEEE International Conference on CAD, November 1993.
  11. B. R. Stanisic, R. A. Rutenbar and L. Richard Carley, “Power Distribution Synthesis for Analog and Mixed-Signal ASICs in RAIL,” Proceedings of the 1993 Custom Integrated Circuits Conference (CICC), May 1993.
  12. S. Mitra, S.K. Nag, R.A. Rutenbar and L.R. Carley, “System-Level Routing of Mixed-SIgnal ASICs in WREN,” Proceedings ACM/IEEE International Conference on CAD (ICCAD’92), November 1992.
  13. J. Cohn, D. Garrod, R. A. Rutenbar, and L. R. Carley, “Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II,” Proceedings 1991 IEEE International Conference on Computer Aided Design (ICCAD’91), Nov. 1991. 
  14. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “KOAN / ANAGRAM II: New Techniques for Device-Level Analog Placement and Routing,” IEEE Journal of Solid State Circuits, vol. 26, no. 3, February 1991.
  15. J. Cohn, D. Garrod, R. A. Rutenbar and L. R. Carley, “New Algorithms for Placement and Routing of Custom Analog Cells in ACACIA,” in Proceedings IEEE Custom Integrated Circuits Conference (CICC’90), May 1990.
  16. D. Garrod, R. A. Rutenbar and L. R. Carley, “Automatic Layout of Custom Analog Cells in ANA­GRAM,” Proceedings ACM/IEEE International Conference on Computer Aided Design (ICCAD’88), November 1988.

 

Modeling, Simulation and Verification

  1. Saurabh K. Tiwary and  Rob A Rutenbar, “Faster, Parametric Trajectory-based Macromodels Via Localized Linear Reductions,'   Proc. ACM/IEEE International Conference on CAD, Nov. 2006.
  2. Saurabh K Tiwary and  Rob A Rutenbar, “On-the-Fly Fidelity Assessment for Trajectory-Based Cir­cuit Macromodels,” Proc. 2006 IEEE Custom Integrated Circuits Conference (CICC 2006), September 2006.
  3. G. Frehse, B. H. Krogh, and R. A. Rutenbar, “Verifying Analog Oscillator Circuits using Forward/ Backward Refinement,"  Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE 06), March 2006.
  4. Saurabh Tiwary, Rob A. Rutenbar, “Scalable Trajectory Methods for On-Demand Analog Macro­model Extraction,” Proc. ACM/IEEE Design Automation Conference, June 2005. (Nominated for Best Paper Award.)
  5. G. Frehse, B. H. Krogh, R. A. Rutenbar, and O. Maler, “Time domain verification of oscillator cir­cuit properties,”  2005 Workshop on Formal Verification of Analog Circuits (a satellite event of ETAPS 2005, April 2005, Edinburgh Scotland).
  6. Smriti Gupta, Bruce Krogh, Rob A. Rutenbar, “Towards Formal Verification of Analog Designs,” Proc. ACM/IEEE Int’l Conference on CAD, Nov. 2004.
  7. S. Mitra, R.A. Rutenbar, L.R. Carley and D.J. Allstot, “Substrate-Aware Mixed-Signal Macro-Cell Placement in WRIGHT,” Proceedings 1994 IEEE Custom Integrated Circuits Conference, May 1994.